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DEDICATED REGISTERS
These are memory locations used inside the HD63B01Y0
microprocessor chip. Full details on how they are used can be found in
the section 6301 MICROPROCESSOR DATA. For
example, to configure one of the spare parallel ports (Port 6) for input
on bits 0-3 and output on bits 4-7 type
HEX F0 16 C!
This writes data hex F0 to address 16, the data direction
register for the port.
NOTES
q Addresses
not shown are external and available for use
q R=Read
only register. W=Write only register (data read back will be meaningless).
R/W= Read/Write register
q The
last column shows data initialised at reset by either the microprocessor
chip hardware or the Forth system.
q Initialisations
not shown indicate indefinite data
| Addr |
Register |
Abbrev |
R/W |
Init |
| 01 |
Port
2 Data Direction Register |
P2DDR |
W |
|
| 03 |
Port
2 Input/Output |
PORT2 |
R/W |
7F |
| 08 |
Timer
Control/Status Register 1 |
TCSR1 |
R/W |
04 |
| 09 |
Free
Running Counter (MSB) |
FRCH |
R/W |
00 |
| 0A |
Free
Running Counter (LSB) |
FRCL |
R/W |
00 |
| 0B |
Output
Compare Register 1 (MSB) |
OCR1H |
R/W |
FF |
| 0C |
Output
Compare Register 1 (LSB) |
OCR1L |
R/W |
FF |
| 0D |
Input
Capture Register (MSB) |
ICRH |
R |
00 |
| 0E |
Input
Capture Register (LSB) |
ICRL |
R |
00 |
| 0F |
Timer
Control/Status Register 2 |
TCSR2 |
R/W |
10 |
| 10 |
Rate/Mode
Control Register |
RMCR |
R/W |
C5 |
| 11 |
Tx/Rx
Control Status Register 1 |
TRCSR1 |
R/W |
2B |
| 12 |
Receive
Data Register |
RDR |
R |
|
| 13 |
Transmit
Data Register |
TDR |
W |
|
| 14 |
RAM/Port
5 Control Register |
RP5CR |
R/W |
E0 |
| 15 |
Port
5 Input/Output |
PORT5 |
R/W |
|
| 16 |
Port
6 Data Direction Register |
P6DDR |
W |
00 |
| 17 |
Port
6 Input/Output |
PORT6 |
R/W |
|
| 19 |
Output
Compare Register 2 (MSB) |
OCR2H |
R/W |
FF |
| 1A |
Output
Compare Register 2 (LSB) |
OCR2L |
R/W |
FF |
| 1B |
Timer
Control/Status Register 3 |
TCSR3 |
R/W |
20 |
| 1C |
Time
Constant Register |
TCONR |
W |
FF |
| 1D |
Timer
2 Up Counter |
T2CNT |
R/W |
00 |
| 1E |
Tx/Rx
Control Status Register 2 |
TRCSR2 |
R/W |
28 |
| 1F |
Chip
test register. Do not access |
TSTREG |
|
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| 20 |
Port
5 Data Direction Register |
P5DDR |
W |
00 |
| 21 |
Port
6 Control/Status Register |
P6CSR |
R/W |
07 |
| 22-27 |
Reserved
by Hitachi |
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